FLC−SIPM: Front-End Chip for SIPM Readout for ILC Analog HCAL

eConf: C050318 : LCWS-2005-0916An integrated front-end chip has been developed to readout the Silicon PM for the ILC analog hadronic calorimeter. It is built around a variable gain low-noise preamplifier followed by a variable peaking-time shaper (20-200 ns), track and hold and multiplexed output. This structure allows to produce single photo electron spectrum with well separated peaks for absolute calibration at fast shaping (40ns) as well as physics signals from the scintillating fibbers (up to 2000 photo-electrons) with a slower shaping (150ns) compatible with the W-Si Electromagnetic Calorimeter DAQ. Besides, an input DAC allows to tune the detector gain by varying the operating voltage by up to 5V. The chip accommodates 18 channels and 1000 circuits have been produced in 2004, the design and the measurement results of which will be presented

Front-end Electronic for the Calice ECAL Physics Prototype

eConf: C050318 : 0902A 18-channel low-noise front-end chip has been designed and produced to read out the 1cm² silicon PIN diodes of the CALICE WSi physics prototype calorimeter. Each channel includes a multi-gain low noise charge preamplifier followed by a bi-gain shaper and a track and hold device. A single output allows reading out every channel at 5 MHz through a multiplexer. Voltage swing is 2.5V with a 5‰ non-linearity. The measured dynamic range on a fixed gain is larger than 13 bits. The gain of the preamplifier can be tuned from 0.3V/pC to 5V/pC with 4 bits. The shaping is done by two fixed-gain shapers (gain 1 and gain 10). Output measured noise is 3000 e- with a detector capacitance of 100pF and a MIP around 42000 e-. Crosstalk is around 1‰. 1000 chips have been produced to equip the physics prototype. Several version of PCB have been designed, taking into account the thickness constraint. A first version with the front-end chip outside the detector has been produced and has been running since January 2005 at DESY, exhibiting an overall MIP/noise ratio of 9. A new thinner version embedding the chip inside the calorimeter has been prototyped and is ready to go in test beam

“ROC” Chips Readout

International audienceThe OMEGA group at LAL has designed 3 chips for ILC calorimeters: one analog (SPIROC) and one digital (HARDROC) for the hadronic one and also one for the electromagnetic one (SKIROC). The readout and the management of these different chips will be explained. To minimize the lines between the ASICs and the DAQ, the readout is made thanks to 2 lines which are common for all the chips: Data and TransmitOn. As the chips are daisy chained, each chip is talking to the DAQ one after the other. When one chip has finished its readout, it starts the readout of the chip just after. Moreover, during this readout, only the chip which is talking to the DAQ is powered: this is made thanks to the POD (Power On Digital) module in the ASIC. In the ILC mode, readout sequence is active during inter bunch crossing (like ADC conversion). Another chip designed for PMM2 R&D program (PARISROC) integrates a new selective readout: that's mean only hit channels are sent to the DAQ in a complete autonomous mode

Dedicated front-end electronics for the next generation of linear collider electromagnetic calorimeter

This paper describes an R&D electronic program for the next generation of linear collider electromagnetic calorimeter. After a brief presentation of the requirements, a global scheme of the electronics is given. Then, we describe the three different building blocks developed in 0.35\mum CMOS technology: an amplifier, a comparator and finally the pipelined AD

A large dynamic range integrated front-end for photomultiplier tubes

A full custom analog CMOS circuit for obtaining a photomultiplier readout with a 16 bit resolution over 7 V has been developed. It is part of the R&D program for the photomultiplier tube front-end readout of the Pierre Auger Observatory northern site. It performs signal duplication and amplification with three gains: 0.15, 1 and 6. Each amplifier has a resolution of 10 bit and can measure signals with durations of several microseconds with a good baseline stability, for an input charge of up to tens of nano-Coulombs. The amplification is performed by current feedback amplifiers with a bandwidth of 60 MHz.The input impedance, adapted to the coaxial cables, is stable over the whole working range. A prototype was submitted in April 2004 and successfully tested. The linearity over the working range is less than 1%. It was also successfully tested on the Auger surface detector element installed at Orsay (comprised of a Cherenkov water tank equipped with Photonis XP1805 9” diameter photomultiplier tubes). The resolution over 7 V is 16.6 bit.This circuit is the first step towards a “system-on-a-chip” (SoC) solution for a photomultplier tube readout equipped with a fast ADC for signal digitization. A setup using a single cable for both the signal and the photomultiplier high voltage power supply was shown to be successful

PARISROC, a Photomultiplier Array Integrated Read Out Chip

PARISROC is a complete read out chip, in AMS SiGe 0.35 !m technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for research (ANR) called PMm2: ?Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles? (ref.ANR-06-BLAN-0186). The ASIC (Application Specific Integrated Circuit) integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC (Analog to Digital Converter) and a 24-bit Counter. The charge measurement should be performed from 1 up to 300 photo- electrons (p.e.) with a good linearity. The time measurement allowed to a coarse time with a 24-bit counter at 10 MHz and a fine time on a 100ns ramp to achieve a resolution of 1 ns. The ASIC sends out only the relevant data through network cables to the central data storage. This paper describes the front-end electronics ASIC called PARISROC.Comment: IEEE Nuclear Science Symposium an Medical Imaging Conference (2009 NSS/MIC

Dedicated front-end electronics for the next generation of linear collider electromagnetic calorimeter

présenté par S. ManenThis paper describes an R&D electronic program for the next generation of linear collider electromagnetic calorimeter. After a brief presentation of the requirements, a global scheme of the electronics is given. Then, we describe the three different building blocks developed in 0.35\mum CMOS technology: an amplifier, a comparator and finally the pipelined AD